The present invention is related to electronic signal conversion, and more particularly to analog to digital converters.
Turning to FIG. 1, a prior art flash analog to digital converter circuit 100 is shown that includes a resistor ladder 130 that generates a number of reference voltage levels for comparison with an input conversion voltage 190 by respective ones of comparators 110. A negative input of each of the comparators is fed by the output of a respective multiplexer 120. Each of the multiplexers 120 selects between six different reference voltages generated by the resistor ladder. While three comparators 110, three multiplexers 120 and a resistor ladder including ten resistors are shown, more than these numbers may be included in the circuit as indicated by marks 195, 196.
As shown, resistor ladder 130 includes a number of resistors 160, 161, 162, 163, 164, 165, 166, 167, 168, 169 that are connected in series between a lower voltage potential 150 and an upper voltage potential 140. Each of the aforementioned resistors generates a distinct reference voltage level that may be chosen for comparison by one of comparators 110. In particular, multiplexer 120a receives upper voltage potential 140, a voltage 170 that is one IR drop below upper voltage reference 140, a voltage 171 that is two IR drops below upper voltage reference 140, a voltage 172 that is three IR drops below upper voltage reference 140, a voltage 173 that is four IR drops below upper voltage reference 140, and a voltage 174 that is five IR drops below upper voltage reference 140. Multiplexer 120a is operable to select one of the aforementioned reference voltage levels to pass to comparator 110a for comparison with an input conversion voltage 190.
Multiplexer 120b receives voltage 172, voltage 173, voltage 174, a voltage 175 that is six IR drops below upper voltage reference 140, a voltage 176 that is seven IR drops below upper voltage reference 140, and a voltage 177 that is eight IR drops below upper voltage reference 140. Multiplexer 120b is operable to select one of the aforementioned reference voltage levels to pass to comparator 110b for comparison with input conversion voltage 190. Multiplexer 120c receives a number of reference voltage levels including lower voltage potential 150, a voltage 179 that is one IR drop above lower voltage potential 150, and a voltage 178 that is two IR drops above lower voltage potential 150. Multiplexer 120c is operable to select one of the aforementioned reference voltage levels to pass to comparator 110c for comparison with input conversion voltage 190.
The above described analog to digital converter provides an effective analog to digital conversion, however, such an approach is relatively expensive in terms of both area and power. A general trend in flash analog to digital converter circuits is to reduce power and area costs through reducing the number of comparators that are utilized in such circuits. An example of such an approach is discussed in Brandt et al., “A 75 mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 12, December 1999. The entirety of the aforementioned article is incorporated herein by reference for all purposes. The article discusses the use of a coarse comparator bank and a fine comparator bank. In operation, the coarse comparator bank identifies in which of four coarse reference segments an analog input lies. Based on this determination, a number of switches are selected to drive a desired reference voltage level range to the comparators in the fine comparator bank. By doing such, the fine comparator bank includes only a limited number of comparators along with a switching network that allows for effective use of the limited number of comparators. In particular, the use of such an architecture reduces the number of comparators to a proportion of 2N/2, where N is the resolution of the analog to digital converter. Thus, for example, only sixty-two comparators are nominally required for a ten bit ADC.
Turning to FIG. 2, an exemplary prior art, four bit subranging analog to digital converter circuit 200 is shown. Analog to digital converter 200 includes a coarse comparator bank 210 consisting of three comparators 212 and a fine comparator bank 230 consisting of three comparators 232. Each of fine comparator bank 230 and coarse comparator bank 210 receive reference values from a resistor ladder 250. Resistor ladder 250 includes resistors 251-266 connected between an upper voltage reference (Vref+) and a negative voltage reference (Vref−). In particular, comparator 212a compares an input voltage 290 with the reference taken between resistor 254 and resistor 255, comparator 212b compares input voltage 290 with the reference taken between resistor 258 and resistor 259, and comparator 212c compares input voltage 290 with the reference taken between resistor 262 and resistor 263. Comparator 232a compares input voltage 290 with one of four references taken between resistor 251 and resistor 252, between resistor 255 and resistor 256, between resistor 259 and resistor 260, and between resistor 263 and resistor 264 as controlled by switches 271, 274, 277, 280; comparator 232b compares input voltage 290 with one of four references taken between resistor 252 and resistor 253, between resistor 256 and resistor 257, between resistor 260 and resistor 261, and between resistor 264 and resistor 265 as controlled by switches 272, 275, 278, 281; and comparator 232c compares input voltage 290 with one of four references taken between resistor 253 and resistor 254, between resistor 257 and resistor 258, between resistor 261 and resistor 262, and between resistor 265 and resistor 266 as controlled by switches 273, 276, 279, 282.
In operation, coarse comparator bank 210 provides a determination of the range in which a fine comparison should be taken. This output is used to select switches 271-282 such that the appropriate reference range is applied to fine comparator bank 230. Then, the output of fine comparator bank 230 and the output of coarse comparator bank 210 are combined to provide the circuit output. In operation, the output of coarse comparator bank 210 must settle before fine comparator bank 230 may be operated. This significantly limits the operating frequency of analog to digital converter 200. While such an approach may work reasonably well for a limited number of bits (i.e., for a limited conversion resolution), for a large number of bits a substantial cost in terms of area is expended on switches corresponding to switches 271-282. Further, where the analog to digital converter circuit is expected to operate quickly, the power consumed by the aforementioned switches can be very significant.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems, circuits and methods for electronic signal conversion.